1. Field of the Invention
The present invention relates to a novel pixel architecture for high speed motion capture CMOS image sensors.
2. Description of Related Art
FIGS. 2A and 2B are circuit schematics of conventional CMOS pixels known as a 3T pixel (for three transistor pixel) and a 4T pixel (for four transistor pixel). The 3T pixel has a reverse biased photodiode coupled between substrate voltage VSUB and the reset gate transistor. When operated, an RST signal applied to the electrode of the reset gate transistor causes a reverse bias to be set on the photodiode equal to output drain voltage VOD less VSUB. Between drain supply VDD and output signal terminal OUT is coupled two series transistors. The drain of a first transistor is coupled directly to VOD, and a gate of the first transistor is coupled to the cathode of the photodiode so that the first transistor operates as a source follower. The source of the source follower transistor is coupled through a row transistor to output terminal OUT. In applications, plural such 3T pixels are coupled to the same output terminal OUT. By selectively applying row address signal ROW to the gate of the selected row transistor, different pixels can be coupled to output terminal OUT. The 4T pixel (FIG. 2B) is like the 3T pixel (FIG. 2A) except that the 4T transistor has a transfer gate transistor coupled between the reset transistor and the photodiode so that a sense node may be created between the transfer transistor and the reset transistor and the sense node may be isolated from the photosite.
There is a need to capture fast changing scenes without the intrusion of a “rolling shutter” artifact while at the same time allowing for antiblooming and/or exposure control functionality. Further, there is a need to operate the pixel without image lag and with minimal fixed pattern noise due to variations in the fat zero signal. Know cameras use external shutters, mechanical or otherwise, to eliminated the rolling shutter artifacts.
U.S. Pat. No. 5,900,623 to Tsang, et al. describes a five transistor pixel with two transistors arranged as a differential pair. However, operation of the Tsang, et al. pixel requires that complementary signals be applied to FETS in a differential configuration, and that photocharge be accumulated on capacitor MCAP at a drain of one of the differentially configured FETS. The Tsang, et al. pixel does not allow for electronically “shuttered” image acquisition.
U.S. Pat. No. 6,115,065 to Yadid-Pecht and Fossum describes a pixel with four transistors and a photogate in a configuration of a 4T pixel. This pixel does not provide protection against a rolling shutter artifact (as described herein) at the same time as antiblooming and exposure control.
U.S. Pat. No. 5,881,184 to Guidash describes a pixel with a transistor to allow resetting of a sense/storage node on a pixel by pixel basis. However, the pixel does not provided antiblooming functionality at the same time as it provides protection against the rolling shutter artifact.
U.S. Pat. No. 6,002,123 to Suzuki describes a 4T pixel. However, the pixel does not provided antiblooming functionality at the same time as it provides protection against the rolling shutter artifact. Further, Suzuki does not describe the hard/soft reset sequences describe in the present patent.
U.S. Pat. No. 5,867,215 to Kaplan describes a CCD spill architecture that allows for enhanced dynamic range. However, the pixel does not provided antiblooming functionality and does not describe the hard/soft reset sequences describe in the present patent.
U.S. Pat. No. 5,760,723 to McGrath et al. describes a CCD spill well architecture that makes use of a fill and spill methodology. However, McGrath et al. do not describe a hard/soft reset methodology that removes image lag by the hard reset and minimizes noise with the soft reset.